This invention relates to a fabrication of Schottky transistors and vertical fuses in integrated circuits. In particular, the invention relates to a Schottky clamped transistor (SCT) having a first metal silicide on all contacts with a second metal silicide displacing the first silicide on at least a portion of the base contact. The invention also provides a vertical fuse having a polycrystalline silicon ("polysilicon") contact to an emitter that improves switching speed and reduces side wall junction capacitance between the emitter and a base.
Numerous processes are now well known for the fabrication of bipolar transistor integrated circuits. Oxide isolated bipolar transistors integrated circuits are also well known, for example, as taught by Douglas Peltzer in U.S. Pat. No. 3,648,125, entitled "Method of Fabricating Integrated Circuits with Oxidized Isolation and the Resulting Structure", hereby expressly incorporated by reference for all purposes.
In addition to the above described "isoplanar" processing technology, the manufacture of both bipolar transistor devices and CMOS devices on a single die and incorporated into a single integrated circuit have been taught in U.S. Pat. No. 4,764,480, issued Aug. 16, 1988 to Vora, entitled "Process for Making High Performance CMOS and Bipolar Integrated Devices On One Substrate With Reduced Cell Size", hereby expressly incorporated by reference for all purposes. The described process uses polysilicon as an interconnect medium to form contacts to desired active areas.
In typical oxide isolated processes of the prior art, an N-type buried layer is diffused into a P-type silicon substrate. An N-type epitaxial layer is then deposited across the upper surface of the substrate. A suitable mask, typically silicon nitride on silicon dioxide, then is formed on top of the epitaxial layer, with regions of the silicon nitride being removed wherever field oxide regions are desired in the epitaxial layer. The epitaxial layer then is oxidized through the openings in the nitride layer to define these field oxide regions. If a recessed field oxide region is desired, a silicon etch is performed prior to oxidation.
In conventional bipolar process technology, the epitaxial layer is then implanted with a P-type dopant to define a base of the bipolar device, and then a heavily doped N-type emitter is diffused within the base region. If a transistor is desired, metal contacts are formed to the emitter, base and collector. The base contact is spaced apart from the emitter contact, while the collector contact relies upon a collector sink of like conductivity type to the buried layer, extending from a surface of the epitaxial layer to the buell known, for example, as taught by Douglas Peltzer in U.S. Pat. No. 3,648,125, entitled "Method of Fabricating Integrated Circuits with Oxidized Isolation and the Resulting Structure", hereby expressly incorporated by reference for all purposes.
In addition to the above described "planar" processing technology, the manufacture of both bipolar transistor devices and CMOS devices on a single die and incorporated into a single integrated circuit have been taught in U.S. Pat. No. 4,764,480, issued Aug. 16, 1988 to Vora, entitled "Process for Making High Performance CMOS and Bipolar Integrated Devices On One Substrate With Reduced Cell Size", hereby expressly incorporated by reference for all purposes. The described process uses polysilicon as an interconnect medium to form contacts to desired active areas.
In typical oxide isolated processes of the prior art, an N-type buried layer is diffused into a P-type silicon substrate. An N-type epitaxial layer is then deposited across the upper surface of the substrate. A suitable mask, typically silicon nitride on silicon dioxide, then is formed on top of the epitaxial layer, with regions of the silicon nitride being removed wherever field oxide regions are desired in the epitaxial layer. The epitaxial layer then is oxidized through the openings in the nitride layer to define these field oxide regions. If a recessed field oxide region is desired, a silicon etch is performed prior to oxidation.
In conventional bipolar process technology, the epitaxial layer is then implanted with a P-type dopant to define a base of the bipolar device, and then a heavily doped N-type emitter is diffused within the base region. If a transistor is desired, metal contacts are formed to the emitter, base and collector. The base contact is spaced apart from the emitter contact, while the collector contact relies upon a collector sink of like conductivity type to the buried layer, extending from a surface of the epitaxial layer to the buried layer. If a fuse is to be formed, the base contact is omitted. If a Schottky clamped transistor is to be formed, metal is used to connect a collector contact with the base contact.
In the past, applications have employed bipolar transistor devices as fuses in a programmable read only memory ("PROM") and in a programmable array logic ("PAL") device, as well as in other types of circuits. Vertical fuses are generally preferred to lateral fuses in these applications due to a smaller size and a greater packing density within an integrated circuit. A fusing action in typical prior art vertical fuses is activated by supplying a sufficiently high current or voltage pulse between an emitter and a collector of a bipolar transistor such that the fuse device is transformed from a floating base NPN transistor "0" to a collector-base diode "1". In a memory of a preferred embodiment, the ohmic contact transforms a bit represented by a transistor from a "0" to a "1" storage element.
Some prior art processes form a polysilicon contact for emitter and collector regions. In conventional processes, the polysilicon is established as a relatively flexible means of contacting and interconnecting various active regions of an integrated circuit. Generally, polysilicon is formed over an entire die, and areas are selectively doped to form contacts to the silicon below, or to form resistive elements, as known in the art.
In providing metal contacts to the polysilicon regions, a refractory metal is deposited over the entire die and reacted wherein a silicide is formed. Typically, titanium ("Ti") is used whereby TiSi is formed. Other refractory metals may be used to produce a silicide, such as platinum silicide ("PtSi"), molybdenum silicide ("MoSi") and tantalum silicide ("TaSi"). Unreacted metal is removed and metallization processes are commenced. When incorporating vertical fuses on the same die as regular transistors, the metallization processes often include the formation of a barrier metal layer titanium-tungsten ("TiW") over the silicide on the transistors before a contact metal is deposited. The barrier metal prohibits the diffusion of contact metal atoms into the polysilicon for transistors, as happens with the contact metal in the vertical fuses. One problem in forming structures having transistors and fuses together is that of minimizing the process effects forming the barrier metal on the transistors without allowing the barrier metal to deposit on the fuses.
In addition to the use of vertical fuses, many integrated circuits benefit from the use of Schottky clamped transistors. These transistors are desirable for their controlled base current. The Schottky clamped transistor is a bipolar transistor using many of the same fabrication steps used to make a bipolar fuse device as above. However, the metal contact scheme necessary for the diode junction between the collector and base of the Schottky clamped transistor requires processing steps that are often incompatible with the fabrication of vertical fuses. For example, it is well known that PtSi is used as the Schottky metal contact in the Schottky clamped transistor, yet PtSi is undesirable in some fuse devices as it increases contact resistance. Furthermore, when Schottky devices and vertical fuses are fabricated on the same substrate, all the contact regions are opened before PtSi is deposited on the substrate surface. PtSi is only intended for the Schottky devices and an etch is used to remove any undesired PtSi from the remaining contacts, especially those on the vertical fuses. This etching is hard to precisely control, and because of such, the unintended overetching leads to shorting of the VV.sub.EBO of both the vertical fuses as well as top-contacted NPN transistors, when included. Furthermore, when fabricating Schottky clamped transistors and fuse devices on the same substrate, the Schottky clamped transistor must be protected from the interconnect metal, such as aluminum, to protect it from the same type of fusing action needed for the fuse device.
Therefore, an improved method for fabricating Schottky transistors and vertical fuse devices as well as improved devices resulting therefrom are desired.